HMC704LP4E【PDF 32/44 页】IC FRACT-N PLL 16BIT 24QFN

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Sheet目录1996

28页 29页 30页 31页 [32页]33页 34页 35页 36页

5 - 38

HMC704LP4E

v03.1211

8 GHz fractionaL-n PLL

For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824

Phone: 978-250-3343

Fax: 978-250-3373

Order On-line at www.hittite.com

Application Support: Phone: 978-250-3343 or apps@hittite.com

table 19. reg 06h SD cfG register

BIT

TYPE

NAME

DEFLT

DEsCRIPTION

[1:0]

R/W

seed select

selects the seed in Fractional Mode

00: 0 seed

01: lsb seed

02: B29D08h seed

03: 50F1CDh seed

Note; Writes to this register are stored in the PLL and are only

loaded into the modulator when a frequency change is executed

and if autoseed Reg06h[13] =1

[3:2]

R/W

Modulator order

select the Delta sigma Modulator Type

0: Reserved

1: Reserved

2: Mode B Offers better out of band spectral performance. Mode B

Required for Exact Frequency Mode.

3: Mode A Offers better in band spectral performance

[6:4]

R/W

Reserved

[7]

R/W

frac_bypass

0: Use Modulator, Required for Fractional Mode,

1: Bypass Modulator, Required for Integer Mode

Note: In bypass fractional modulator output is ignored, but frac-

tional modulator continues to be clocked if frac_rstb =1, Can be

used to test the isolation of the digital fractional modulator from the

VCO output in integer mode

[8]

R/W

autoseed

1: loads the modulator seed (start phase) whenever the frac regis-

ter is written

0: when frac register write changes frequency, modulator starts

with previous contents

[9]

R/W

clkrq_refdiv_sel

selects the modulator core clock source- for Test Only

1: VCO divider clock

0: Ref divider clock

Ignored if bits [10] or [21] are set

[10]

R/W

Modulator Core Clk select

0 - Modulator auxclk, 1- Modulator VCO Clock delay

[11]

R/W

frac_rstb

0: disable Modulator, use for Integer Mode or Integer Mode with

CsP

1: Enable Modulator Core, required for Fractional Mode, or Integer

isolation testing

[12]

R/W

Reserved

[13]

R/W

Reserved

[15:14]

R/W

Reserved

[17:16]

R/W

Reserved

Program to 3 decimal “11” binary

[18]

R/W

BIsT Enable

Enable Built in self Test

[20:19]

R/W

RDIV BIsT Cycles

0:1023

1:2047

2:3071

3:4095

[21]

R/W

Reserved

[22]

R/W

Reserved

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